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Nordic Semiconductor /nrf52 /SAADC /INTENCLR

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Interpret as INTENCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)STARTED 0 (Disabled)END 0 (Disabled)DONE 0 (Disabled)RESULTDONE 0 (Disabled)CALIBRATEDONE 0 (Disabled)STOPPED 0 (Disabled)CH0LIMITH 0 (Disabled)CH0LIMITL 0 (Disabled)CH1LIMITH 0 (Disabled)CH1LIMITL 0 (Disabled)CH2LIMITH 0 (Disabled)CH2LIMITL 0 (Disabled)CH3LIMITH 0 (Disabled)CH3LIMITL 0 (Disabled)CH4LIMITH 0 (Disabled)CH4LIMITL 0 (Disabled)CH5LIMITH 0 (Disabled)CH5LIMITL 0 (Disabled)CH6LIMITH 0 (Disabled)CH6LIMITL 0 (Disabled)CH7LIMITH 0 (Disabled)CH7LIMITL

CH0LIMITH=Disabled, CH3LIMITH=Disabled, STOPPED=Disabled, CH5LIMITH=Disabled, END=Disabled, CH6LIMITL=Disabled, CH2LIMITL=Disabled, CH1LIMITH=Disabled, CH7LIMITL=Disabled, CH3LIMITL=Disabled, CH7LIMITH=Disabled, CH4LIMITL=Disabled, CH0LIMITL=Disabled, CH5LIMITL=Disabled, CALIBRATEDONE=Disabled, RESULTDONE=Disabled, DONE=Disabled, CH4LIMITH=Disabled, CH2LIMITH=Disabled, CH1LIMITL=Disabled, CH6LIMITH=Disabled, STARTED=Disabled

Description

Disable interrupt

Fields

STARTED

Write ‘1’ to Disable interrupt for STARTED event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
END

Write ‘1’ to Disable interrupt for END event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
DONE

Write ‘1’ to Disable interrupt for DONE event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
RESULTDONE

Write ‘1’ to Disable interrupt for RESULTDONE event

0 (Disabled): Read: Disabled

1 (Enabled): Read: Enabled

1 (Clear): Disable
CALIBRATEDONE

Write ‘1’ to Disable interrupt for CALIBRATEDONE event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
STOPPED

Write ‘1’ to Disable interrupt for STOPPED event

0 (Disabled): Read: Disabled

1 (Enabled): Read: Enabled

1 (Clear): Disable
CH0LIMITH

Write ‘1’ to Disable interrupt for CH[0].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH0LIMITL

Write ‘1’ to Disable interrupt for CH[0].LIMITL event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH1LIMITH

Write ‘1’ to Disable interrupt for CH[1].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH1LIMITL

Write ‘1’ to Disable interrupt for CH[1].LIMITL event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH2LIMITH

Write ‘1’ to Disable interrupt for CH[2].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH2LIMITL

Write ‘1’ to Disable interrupt for CH[2].LIMITL event

0 (Disabled): Read: Disabled

1 (Enabled): Read: Enabled

1 (Clear): Disable
CH3LIMITH

Write ‘1’ to Disable interrupt for CH[3].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH3LIMITL

Write ‘1’ to Disable interrupt for CH[3].LIMITL event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH4LIMITH

Write ‘1’ to Disable interrupt for CH[4].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH4LIMITL

Write ‘1’ to Disable interrupt for CH[4].LIMITL event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH5LIMITH

Write ‘1’ to Disable interrupt for CH[5].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH5LIMITL

Write ‘1’ to Disable interrupt for CH[5].LIMITL event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH6LIMITH

Write ‘1’ to Disable interrupt for CH[6].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH6LIMITL

Write ‘1’ to Disable interrupt for CH[6].LIMITL event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH7LIMITH

Write ‘1’ to Disable interrupt for CH[7].LIMITH event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CH7LIMITL

Write ‘1’ to Disable interrupt for CH[7].LIMITL event

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled

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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

  3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data